module count_16(clk,clr,SW1,HEX0,HEX1,HEX2,HEX3);
	input [0:0]clr,SW1,clk;
	output [0:6]HEX0,HEX1,HEX2,HEX3;
	reg [15:0]q;
	wire [3:0]addr3,addr2,addr1,addr0;
	always @(posedge clk)
		begin
			if(!clr)
				q<=0;
			else
				begin
					if(SW1==1'b1)
						q<=q+16'b0000000000000001;
					else
						q<=q;
				end
		end
	assign {addr3,addr2,addr1,addr0}=q;

	counter_16  u1(addr3,HEX3);
	counter_16  u2(addr2,HEX2);
	counter_16  u3(addr1,HEX1);
	counter_16  u4(addr0,HEX0);

endmodule

module counter_16(ST,HEX);
	input [3:0]ST;
	output reg[0:6] HEX;

	always @(*) begin
		case(ST)
			4'b0000: HEX=~7'b1111110;
			4'b0001: HEX=~7'b0110000;
			4'b0010: HEX=~7'b1101101;
			4'b0011: HEX=~7'b1111001;
			4'b0100: HEX=~7'b0110011;
			4'b0101: HEX=~7'b1011011;
			4'b0110: HEX=~7'b1011111;
			4'b0111: HEX=~7'b1110000;
			4'b1000: HEX=~7'b1111111;
			4'b1001: HEX=~7'b1111011;
			4'b1010: HEX=~7'b1110111;
			4'b1011: HEX=~7'b0011111;
			4'b1100: HEX=~7'b1001110;
			4'b1101: HEX=~7'b0111101;
			4'b1110: HEX=~7'b1001111;
			4'b1111: HEX=~7'b1000111;
		endcase
	end
endmodule